Shibagaki et al., Japanese Patent Publication 2006179888A, discloses a two layer interlayer film for a chip carrier. A high viscosity layer of curable resin composition containing 5-45% inorganic filler and a low viscosity layer curable resin composition containing 35-75% inorganic filler are disclosed.
Mizukai et al., Japanese Patent Publication 2006051469, discloses a dry resist photosensitive material manufacturing method that manufactures a dry resist photosensitive material having multiple photosensitive layers formed on a support, characterized by the fact that the 2 or more photosensitive layers are formed at the same time by coating two or more kinds of coating solutions on a support by using a simultaneous multi-layer coating apparatus at the same time, followed by drying.
Nakamura et al., U.S. Pat. No. 6,376,053, discloses an interlaminar adhesive film for chip carriers, the adhesive film having at least two layers, and a method for preparing multilayer chip carriers.
A multi-layer chip carrier typical of the art is shown schematically in FIG. 1. A multi-layer chip carrier, 100, typically includes a core layer, 102, often but not necessarily an epoxy-fiberglass composite, upon which are adheringly disposed several discrete conductive pathways, 103, to form a first layer. The conductive pathways, 103, and the substrate surface between conductive pathways, 104, are completely encapsulated by a two layer dielectric build-up layer, 105a and 105b, Disposed upon the top surface of the dielectric build-up layer, 105b, is a second layer of conductive pathways, 106. Also shown in FIG. 1 is a conductive via, 107, connecting a conductive pathway in the first layer to a conductive pathway in the second layer. The purpose of the structure, 100, is to provide circuitry for one or more integrated circuit chips, 108, mounted on the chip carrier. In common commercial use, the two layer dielectric build-up layer depicted in FIG. 1 is replaced by a single homogeneous layer.
The dielectric build-up layer, 105a and 105b, in a multi-layer chip carrier, 100, performs several functions. When the dielectric build-up layer is a two layer structure as depicted in FIG. 1, the bottom portion of the dielectric build-up layer, 105a, adheringly conforms to the discrete conductive pathways, 103, and the substrate surface between them, 104, with a low coefficient of thermal expansion in order to avoid delamination during processing. The top surface of the upper portion of the dielectric build-up layer, 105b, provides a high level of adhesion for the second layer of conductive pathways, 106. Low coefficient of thermal expansion (CTE) is desired.
The bottom portion, 105a, is formable during preparation in order to completely encapsulate the substrate surface, 104, and the first layer of conductive pathways, 103. However, after encapsulation the dielectric build-up layer exhibits a low coefficient of thermal expansion in order to prevent delamination. This is generally accomplished in the art by employing a curable resin for the dielectric build-up layer.
The direction of the electronics industry is to ever smaller circuit components. Reduction in the spacing intervals and size of the conductive pathways places ever greater demands on the coefficient of thermal expansion of the dielectric build-up layer in order to prevent delamination. In typical commercial practice, the surface of the dielectric build-up material is roughened in preparation for deposition of the next layer of conductive material. If the surface features of the roughened material are large enough, they will lead to excessive non-uniformity in the geometry of the next layer of conductive pathways resulting in impedance variations that degrade the processability of high frequency signals.
Lower CTE can be achieved by increasing the filler content. But higher filler content can lead to a higher surface roughness. Nakamura et al. address this problem by using a two-layer film. However, the interface between the layers can be a locus of stress concentration with possible delamination. In addition, the production cost for a multilayer dielectric build-up layer according to the method of the art is high.